8 research outputs found

    The application of genetic algorithms to high-level synthesis

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    Overlapped scheduling techniques for high-level synthesis and multiprocessor realizations of DSP algorithms

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    Algorithms that contain computations that can be executed simultaneously, offer possibilities of exploiting the parallelism present by implementing them on appro priate hardware, such as a multiprocessor system or an application-specific inte grated circuit (ASIC). Many digital signal processing (DSP) algorithms contain in ternal parallelism and are besides meant to be repeated infinitely (or a large number of times). These algorithms, therefore, not only have intra-iteration parallelism (between operations belonging to the same iteration) but inter-iteration parallelism (between operations belonging to different iterations) as well [Par9 1]

    High-Level Synthesis Scheduling and Allocation using Genetic Algorithms

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    In this article a scheduling method is presented which is capable of allocating supplementary resources during scheduling. This makes it very suitable in synthesis strategies based on lower bound estimations techniques. The method is based on genetic algorithms. Special coding techniques and analysis methods are used to improve the runtime and quality of the results. The scheduler can easily be extended to coverother architectural issues and (for example) providesways to make trade-offs between functional unit allocation and register allocation. Experiments and comparisons show high quality results and fast run times that outperform results produced by other heuristic scheduling methods 1 Introduction High-level synthesis translates behavioral descriptions into digital network structures. During this translation the cycle steps in which operations start their execution must be determined (scheduling problem). A schedule induces a resource allocation (because some operations are execut..

    A Code-Motion Pruning Technique for Global Scheduling

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    In the high--level synthesis of ASICs or in the code generation for ASIPs, the presence of conditionals in the behavioral description represents an obstacle to exploit parallelism. Most existing methods use greedy choices in such a way that the search space is limited by the applied heuristics. For example, they might miss opportunities to optimize across basic block boundaries when treating conditional execution. We propose a constructive method which allows generalized code motions. Scheduling and code motion are encoded in the form of a unified resource--constrained optimization problem. In our approach many alternative solutions are constructed and explored by a search algorithm, while optimal solutions are kept in the search space. Our method can cope with issues like speculative execution and code duplication. Moreover, it can tackle constraints imposed by the advance choice of a controller, such as pipelined--control delay and limited branch capabilities. The underlying timing m..
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